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现有美国CISCO公司设在上海的Data center business unit需要招聘数位工程师，负责人之一为我校校友，具体职位要求描述如下。感兴趣的校友们可直接联系。

Cisco Systems Inc. 简介：
思科系统公司1984年成立于美国。它是全球网络互联解决方案的领先厂商，其提供的解决方案是世界各地成千上万的公司、大学、企业和政府部门建立互联网的基础，用户遍及电信、金融、服务、零售等行业以及政府部门和教育机构等。思科系统公司目前在全球拥有35000 多名雇员。

Cisco Storage Networking Solutions are designed to deliver an open standards-based infrastructure that allows companies to better utilize and share storage resources, improve business continuance, and lower the cost of ownership for storage. The solutions are developed from comprehensive combinations of technologies, products, and partnerships. Cisco storage networking solutions encompass the following array of solution areas: Storage Consolidation in the Data Center, Mid-Range and Small/Medium Enterprises and Departmental Servers, and Business Continuance Solutions

如您具有适合的背景，对此工作机会感兴趣，请发简历给：思科系统公司高级经理陈清华先生：cisco.job@gmail.com 。发邮件时请在主题栏中注明您申请哪个职位。

Position 1: 　Hardware Engineer - ASIC Design for Test (DFT) Engineer
职位描述:
Target Number:4
Location:Shanghai

Job Description
Hardware Engineers who participate in the design of complex, high performance and high integration ASICs used in Cisco storage/data center switch products. Implement Design for Test strategy into the ASICs and responsible for ASIC DFT sign off. Participate in driving new DFT methodology and solutions to improve quality of the ASIC, reliability and in system test and debug capability.

Daily responsibilities include:
- Implement basic DFT schemes in terms of BIST, scan, boundary scan on ASICs.
- Generate tests which achieve highest possible ASIC component test coverage with lowest overhead.
- Verify all DFT logics and test patterns with simulation and static timing analysis tool.
- Implement and verify advanced DFT logics like logic BIST, high speed interface test logic etc.
- Participate in new DFT methodology discussion and solution generation.
- Work with ASIC design team in ASIC bring up.

Skills Required
- Good knowledge in Design for Test in general. Understand the concepts of BIST, SCAN, Boundary Scan, ATPG.
- Experience in ASIC DFT design, Testability, and Reliability issues.
- Hands on familiarity with various ASIC DFT analysis, synthesis, and verification tools.
- Familiar with fault coverage and board/system testability analysis and enhancement technique, DFT economics analysis/justification technique.
- Hands on knowledge of simulation and verification debug tools.
- Good knowledge of test engineering in terms of ASIC test program generation, understanding of testers and associated hardware is a plus.
- Working knowledge using Verilog HDL languages and tools, scripting and programming languages (Perl, TCL, C and C++).
- Excellent written and verbal communications, team and people skills.

Educational Background
Typically requires MSEE/CS combined with 3-4 years experience, or BSEE/CS combined with 4-7+ yrs experience.

Position 2: 　Hardware Engineer-ASIC Verification Engineer
职位描述:

Target Number:1
Location:Shanghai

Job Description
Participate in the design and verification of complex, high performance and high integration ASICs used in Cisco Switch and Router.
Responsibilities include:
Detail design specification and test plan development.
RTL logic design, synthesis and timing closure.
Module and full chip verification, formal verification and equivalence checking.
Work with cross-functional teams (hardware, software, diagnostics, signal integrity group).
Assist in prototype bring up and verification in the lab.

Skills Required
Experience in high performance ASIC design experience from start to finish.
Good understanding in ASIC methodologies and flows.
Working knowledge using HDL languages and tools, scripting and programming languages (Perl, TCL, C and C++).
Excellent written and verbal communications in English, team and people skills.
Self motivated, ability to work independently with minimal supervision and provides leadership role.
Networking knowledge preferred.

Educational Background
Typically requires MSEE/CS combined with 3-4 years experience, or BSEE/CS combined with 4-7+ yrs experience.

Position 3: 　Electrical Engineer - PCB Layout and Design
职位描述:

Target Number:4
Location:Shanghai

Job Description
As part of high speed board design team, responsible for high speed, high density printed circuit board physical layout design for networking products. Work closely with PCB fabrication house and engineers from board design, signal integrity and manufacturing groups to perform new or cost reduction PCB boards. You will be responsible for all aspects of PCB layout tasks including parts placement, routing, verification, and creating final design outputs.

Skills required
• 3-5 years of experience working with Cadence Allegro tools. Concept schematic capture experience is a plus.
• Proficiency with all aspects of PCB design
• Strong experience in designing multi-layer, high density designs utilizing 16 to 24 layers with 1500 or more components.
• Experience in high speed routing requirements.
• Good knowledge of signal integrity requirement and noise / crosstalk prevention
• Familiar with current industry Design for Test (DFT) and Design for Manufacturing (DFM) practices.
• Experience in creating pad stacks and component geometries.
• Basic knowledge of electronic manufacturing procedures and materials.
• Self starter with strong organizational, communications and interpersonal skills, with the ability to work on short-cycle design projects.
• Good interpersonal skill, ability to work effectively in a team environment.
• Fluent English in speaking, reading and writing

Position 4: 　Hardware Engineer - ASIC Design
职位描述:

Target Number:3-4

Job Description
Participate in the design and verification of complex, high performance and high integration ASICs used in Cisco Switch and Router.
Responsibilities include:
Detail design specification and test plan development.
RTL logic design, synthesis and timing closure.
Module and full chip verification, formal verification and equivalence checking.
Work with cross-functional teams (hardware, software, diagnostics, signal integrity group).
Assist in prototype bring up and verification in the lab.

Skills Required
Experience in high performance ASIC design experience from start to finish.
Good understanding in ASIC methodologies and flows.
Working knowledge using HDL languages and tools, scripting and programming languages (Perl, TCL, C and C++).
Excellent written and verbal communications in English, team and people skills.
Self motivated, ability to work independently with minimal supervision and provides leadership role.
Networking knowledge preferred.

Educational Background
Typically requires MSEE/CS combined with 3-4 years experience, or BSEE/CS combined with 4-7+ yrs experience.

Position 5: 　Software Engineer
职位描述:

Target Number:4
Location:Shanghai

Job Description & Skills Required
SW engineers participating in Cisco storage/data center switches development in device driver, Linux/kernel and Diagnosis.
1.Hands-on C and C++, including STL programming in Linux or Unix environment.
2.2+ years industrial experience in multi-processor, multi-process, and multi-thread programming. Familiar with IPC and synchronization.
3.Familiar with make tools, shell language, CVS/Clearcase and GDB. Familiar with KGDB is a plus.
4.Familiar with embedded system, device driver and register level programming. Experienced with Linux kernel and Linux device driver model is very desirable.
5.Must be speaking fluent English & a team player.
6.Must be comfortable with large scale team based SW development and frequent inter-group and/or inter-company communication.
7.Experienced with ASIC verification, simulation or BIOS development is a plus.
8.Hi-end networking switch/router SW development experience is a plus.
9.Technical leadership experience is a plus.
10.Candidates should feel comfortable with fast-paced team work SW development and inter-group/company communication.
11.Fluency in English is required.

Educational Background
Typically requires Master degree or compatible combined with 2-8 years industrial experience


Position 6: 　Electronic Design Engineer
职位描述:

Target Number:4
Location:Shanghai

Job Description
As key member of Cisco System hardware team, the individual will define and design next generation Fibre Channel and Ethernet high end switch family. Responsibilities include system and board level specification, schematic capture based on Cadence tool, FPGA design using Verilog HDL, ASIC/System level bring up in the lab, working with Signal Integrity group for high speed PCB design and transferring knowledge to manufacturing engineer into production. The individual is expected to bring up the system to work with multiple groups including ASIC/Signal Integrity/SW/Diag/Mfg to resolve any design issues. Positive working attitude and good communication skills are essential to this position.

Skills Required
• High speed board design with CPU subsystem
• Hands on knowledge of lab equipment and techniques for hardware debugging
• Good spoken and written English skills

Educational Background
B.S.E.E required, M.S.E.E preferred
Minimum 3-5 years related industry experience



Position 7: 　Electrical Engineer – Signal Integrity and High Speed Design

职位描述:
Target Number:4
Location:Shanghai

Job Description
As part of signal integrity and high speed design technology team, design and analyze high speed analog/digital circuits for networking products, with emphasis on high speed signal and power analysis (especially timing and noise) of ASICs and printed circuit boards.

Model/simulate/characterize high speed systems, including high speed I/Os, chip packages, printed circuit boards, and system interconnects. Overcome the challenge of ultra-high data rate, wide buses, multiple clocks, and cutting-edge technology. Seize the opportunity for circuit design innovation when faced with the new challenges brought by the Multi-Gbps serdes products.

Respond to the group's strong focus on present and next-generation products with a commitment to automated processes and tool implementations.

Skills Required
• Proficiency with spice (or equivalent) circuit simulation, 3D field-solver and time/frequency domain analysis
• Experience with IBIS and SPICE simulation tools. Experience with SpecctraQuest , XTK, ADS, ICS and HSPICE a plus
• Experience with 2D, 3D or High Frequency Field Solvers is required.
• Familiarity with high speed serdes design, PLL design and LVDS, LVPECL, CML and other high-performance I/O technologies.
ASIC design experience with I/O selection and simulation/validation, and power noise analysis
• Solid background on transmission line theory are necessary
• Experience correlating simulation results with lab measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers is a plus.
• Strong programming skill with Perl or other script language for process automation
• Self motivation, teamwork and strong communication skills are essential
• Fluent English in speaking, reading and writing

Educational Background
Typically requires MSEE/CS or higher combined with 3-5+ years of related experience, or BSEE/CS combined with 5-7+ yrs related experience.